(1) Field of the Invention
The present invention relates to processes used to fabricate semiconductor devices, and more specifically to a method used to create a dual damascene opening, in an insulator layer, used to accommodate copper interconnect, and copper via structures.
(2) Description of the Prior Art
The use of sub-micron features, or micro-miniaturization, has allowed the semiconductor industry to increase device density for very large scale integrated, (VLSI), semiconductor chips. The evolution to micro-miniaturization has been highlighted by advances in specific semiconductor fabrication disciplines such as photolithography, and dry etching. The development of mode sophisticated exposure cameras, as well as the use of more photo-sensitive materials, have allowed sub-micron images, in photoresist layers, to be routinely obtained. In addition the advent of advanced dry etching tools, and processes, have in turn allowed the sub-micron images, in masking photoresist layers, to be successfully transferred to underlying materials, used in the fabrication of VLSI chips. However to continue to decrease the size of semiconductor chips, specific process or structural innovations, are also needed, in addition to the advances in specific semiconductor fabrication disciplines. One such process innovation has been the use of dual damascene patterning, for attainment of metal lines and metal vias. The dual damascene procedure features the creation of a pattern, opened in an insulator layer, with the dual damascene pattern comprised of an underlying narrow diameter opening, and a wider diameter, overlying opening. Filling of the dual damascene opening, in the insulator layer, with metal, results in a metal structure comprised of a metal interconnect structure, located in the wider diameter opening, overlying a metal via structure, located in the narrower diameter opening, in the dual damascene opening. The dual damascene procedure, in which both metal interconnects, and metal vias, are formed using a single metal fill, and only one metal patterning, or removal procedure, offers advantages over conventional procedures, in which a metal fill, and a metal patterning procedure, would have to be individually formed for both the metal via structure, and the metal interconnect structure.
A critical step, used for creation of a dual damascene opening, is the ability to form, or to terminate, the wider diameter opening, in a top portion of an insulator layer, without transferring this wider diameter opening, to the bottom portion of the insulator layer, where the narrow diameter opening is to be formed. One method used to address this concern is the use of a stop layer, which will subsequently reside between a first interlevel dielectric, (ILD), layer, and a second ILD layer. After forming the desired narrow diameter opening, in the stop layer, which resides on the unetched lower, or first, ILD layer, a second, or upper ILD layer is deposited. A photoresist shape, featuring the wider diameter opening, is used as a mask to create the wider diameter opening, in the second ILD layer, exposing the stop layer, which is comprised with the narrow diameter image. A selective dry etch procedure, is used to form the wide diameter opening, in the second ILD layer, while the stop layer allows the narrow diameter opening, in the stop layer, to be transferred to the underlying first ILD layer, exposed in the narrow diameter opening, in the stop layer. However to successfully prevent unwanted etching of the first ILD layer, a thick stop layer, exhibiting a low removal rate in the dry etching process used for the insulator etching, is employed. Therefore if silicon oxide, with a low dielectric constant is used, for both of the ILD layers, the stop layer used is then usually comprised of silicon nitride, exhibiting a high dielectric constant, however allowing the desired dry etching selectivity to be realized. However since a thick, silicon nitride, stop layer, with a dielectric constant of about 7, is needed, unwanted capacitance results, increasing RC delays, and degrading device performance.
This invention will describe a novel process for forming a dual damascene opening, in ILD layers, to be used to accommodate metal interconnect, and metal via structures. However this invention will feature a reduction in the total thickness of the silicon nitride stop layer, when compared to prior arts, using thicker silicon nitride layers, thus minimizing capacitance. This invention will feature the use of multiple silicon nitride stop layers, strategically placed between silicon oxide, insulator layers, however still thinner, and thus less performance degrading, than counterparts using a single, but thicker, silicon nitride stop layer. The insulator stack, to be subsequently patterned to obtain the dual damascene opening, is comprised of a lower, or first ILD layer, to subsequently contain the narrow diameter via hole, however a thin, first silicon nitride layer, is used to separate a lower, and an upper portion, of the first ILD layer. The insulator stack is also comprised of an upper, or second ILD layer, overlying a second silicon nitride stop layer, which in turn resides on the top surface of the upper portion, of the first ILD layer. This configuration allows selective RIE procedures, to create a wide diameter opening in the second ILD layer, and in the second silicon nitride layer, while creating the desired narrow diameter opening in the first ILD layer, including the first silicon nitride stop layer. The sum of the thicknesses of the silicon nitride layers, is less than for counterpart, dual damascene processes, using a thicker, single silicon nitride stop layer. Prior art, such as Avanzino et al, in U.S. Pat. No. 5,686,354, as well as Huang et al, in U.S. Pat. No. 5,635,423, describe dual damascene processes, however these prior art do not show the multiple stop layers, used in the present invention, offering less capacitance than counterparts described using a thicker, single silicon nitride stop layer.